1. Field of the Invention
The present invention relates to the field of electronic devices and the transfer of data there between and, in particular, to providing a host controller and host controller driver interface to microprocessor based embedded systems for interconnecting devices via a serial bus. More specifically, the present invention relates to a Universal Serial Bus (USB) host controller and host controller driver interface for embedded systems that employ batched data transfer.
2. Description of the Related Art
Electronic devices are often electrically connected to one or more other electronic devices. For example, microprocessor based systems, such as personal computers, are often connected to one or more peripheral devices such as printers, scanners, graphics tablets, digital cameras and the like. The connection to peripheral devices can take place via a number of known serial or parallel interfaces.
The Universal Serial Bus (USB) is one standardized serial interface that has been developed to offer flexible, high, moderate and low-speed interconnections between a host device and external, peripheral devices. USB was developed to accomplish three main goals: connection of a microprocessor based system to a telephone system, plug-and-play of peripheral devices in a hot swappable manner, and ready expansion of a microprocessor based system""s peripheral connectivity.
USB employs a four-wire connector. Two wires supply power (up to 500 mA at 5 vdc) and the other two wires form a twisted-pair, differential data line. USB employs a master-slave architecture with a tiered-star topology. One or more hubs can be connected to a host or root tier to expand the capacity of a USB system. Hubs can also be connected to other hubs to further expand the system. A single USB host can support up to 127 separate devices.
USB currently supports data transfer at a high speed of 480 Mbps, a full speed of 12 Mbps, and a low speed of 1.5 Mbps data rate. There are four types of USB transfers: isochronous, bulk, interrupt and control. Isochronous transfer is not error checked as the need for uninterrupted data transfer at a given data rate overrides the need for error-free transmission. The other three types of transfer contains error-checking mechanisms, data sequence toggle sequences and retry sequences to guarantee error-free data transfer.
A USB system has a single USB host. FIG. 1 shows four layers of a typical USB system. These areas are the Client Software/USB Driver, Host Controller Driver (HCD), Host Controller (HC), and USB Device. The Client Software/USB Device and Host Controller Driver are implemented in software. The Host Controller and USB Device are implemented in hardware. The Host Controller Driver and Host Controller work in tandem to transfer data between client software and a USB device. In the prior art, as described in the two industry standard host specification, the xe2x80x9cUniversal Host Controller Interface (UHCI) Design Guidexe2x80x9d Revision 1.1 published by the Intel Corporation, and the xe2x80x9cOpenHCI: Open Host Controller Interface Specification for USB,xe2x80x9d (OHCI) Revision 1.0a, published by Compaq, Microsoft and National Semiconductor, to achieve high transfer rates on USB, the Host Controller requires a bus interface with bus master capability, such as a Peripheral Component Interface (PCI) bus, to interface with the CPU. Bus mastering requires that more than one device be able to control the data over a bus. Generally, a microprocessor must relinquish control of the bus to another device to allow this to occur.
However, there is a need for a USB Host Controller for embedded systems and microprocessors which do not have a bus interface with bus mastering capability such as a PCI bus. Such a USB Host Controller is referred to as an embedded USB Host Controller which can be interfaced via a standard processor bus interface to any microprocessor, microcontroller, digital signal processor, FPGA processor or any other processor (hereafter referred to as microprocessor). In the prior art, these embedded Host Controllers suffer the shortcoming of low data transfer rate and frequent interrupts to the microprocessor because the microprocessor is interrupted every transaction. Without the bus mastering capability, prior art embedded USB host controllers interrupt the microprocessor for each transaction to report the status of the transaction to the microprocessor, and for the microprocessor to process the just finished transaction, read data from and/or write data into the USB host controller, and prepare and dispatch the next transaction.
Moreover, each interrupt of the microprocessor involves an interrupt latency period. The latency period is the time during which the microprocessor stores the data and status conditions related to task at hand, before it can attends to the request of the USB host. An example timing diagram for the interaction of the microprocessor and a prior art embedded USB host controller showing the interrupt latency period is illustrated in FIG. 2
The interrupt latency period and the interrupt recovery period waste the microprocessor""s time. The USB bus is idle during both the interrupt latency period and the period for the microprocessor to process the current transaction and prepare for the next transaction. That is, there is no data on the USB bus, which results in very low data throughput. The process also slows the microprocessor system as the microprocessor must cease operating on whatever task before the interrupt, attends to the USB host controller, and then recover its working environment to pick up again where it was before.
More specifically, the microprocessor must typically take time to store the registers and context it was working on when it received the interrupt and subsequently retrieve the registers and context and resume processing it upon completion of the task requested by the USB interrupt. The time to cease operation, store the registers and context, and then later retrieve the registers and context and resume processing contributes greatly to the increased inefficiency of the microprocessor during USB interrupts. This can significantly reduce the throughput of the USB connection, as well as the performance of the microprocessor system, below optimum.
OHCI and UHCI host controllers overcomes this problem using reverse bus mastering, such as that provided by a known PCI bus, and equip the host controller with the capability to process sequentially one-by-one a list of transactions scheduled in the microprocessor""s system memory. In this method, upon each transaction, the USB host controller uses the reverse bus master mechanism to access the system memory, processes the transaction, exchanges data with the system memory, and start the next transaction, all without interrupting the microprocessor. While this method does significantly improve the throughput of the USB, it is not applicable to many embedded systems where there is no reverse bus mastering mechanism either due to cost reasons, architectural or software considerations.
From the foregoing, it will be appreciated that there is a need for a system that permits more efficient USB transfers in an embedded system. To this end, there is a need for an improved system that reduces the interrupts to microprocessor and improves the data throughput on USB for a host system having an embedded USB architecture.
The aforementioned needs are satisfied by the present invention which in one aspect comprises a USB host controller system for interfacing between at least one USB device and a host processor. The system comprises a host controller that transfers USB transactions between at least one USB device and a host processor. The system further includes at least one memory associated with the host controller, wherein the host controller stores the information indicative of a plurality of USB transactions in the memory and executes a plurality of stored USB transactions in a single batch so as to reduce the overall resource demands on the host processor to execute the USB transactions and to increase data throughput on the USB.
In another aspect, the invention comprises a method of interfacing a plurality of USB device with a host processor. The method comprises assembling a first batch of USB transactions in a memory, sequentially executing each of the USB transactions of the first batch in the memory and sending an interrupt signal to a host processor indicating that the first batch of transactions has been completed so that the host processor is interrupted less thereby reducing the overall resource demand on the host processor during execution of the first batch.
In yet another aspect, the invention comprises a USB host controller that is adapted to receive and assemble information indicative of a plurality of USB transactions from a host processor wherein the USB host controller executes an assembled batch of a plurality of USB transactions upon meeting a certain condition and wherein the host processor is informed of the availability of the status of the plurality of transactions upon completion of the batch to thereby reduce the overall resource demand on the host processor during execution of the batch of USB transactions.
In yet another aspect, the invention comprises a USB system that comprises a host microprocessor, at least one memory associated with the host microprocessor and an embedded microprocessor bus whose bus master for memory access is the host microprocessor. In this aspect, the USB system further comprises an embedded USB host controller that sends interrupt signals to the host microprocessor such that the host microprocessor in response to the interrupts manipulates data in the at least one memory such that the USB host stack associated with the USB system that is designed to be used with a bus that is controllable by the USB host controller can be mused with the embedded USB host controller.